Interface effects and dielectric mismatch in ultrathin silicon on insulator films

The role of interface states and dielectric mismatch is studied in ultrathin P-doped silicon-on-insulator (SOI) films with thickness of the device layer ($H_{SOI}$) varying from 30 to 8 nm and dopant concentration ($n_{D}$) ranging from 10$^{18}$ to nearly 10$^{20}$ cm$^{-3}$. P concentration is determined by Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS). Sample resistivity ($ρ$), carrier concentration ($n_e$), and mobility ($μ_e$) are extracted by combining sheet resistance and Hall measurements in van der Pauw configuration. When $H_{SOI}$ = 30 nm, transport properties at room temperature are fully compatible with those of a similarly doped bulk Si. Progressive 2D confinement by reduction of $H_{SOI}$ below 30 nm results in a reduction of the carrier concentration and a concomitant degradation of $μ_e$. These effects, which are steadily enhanced decreasing $n_D$, are attributed to non-passivated interface states at the SiO$_2$/Si interface and can be significantly mitigated by high temperature rapid thermal oxidation (RTO). The effectiveness of this approach was verified by electron-paramagnetic resonance (EPR) spectra and capacitance-voltage (CV) measurements, which allowed the assessment of the quality of the RTO-SiO$_2$/Si interface and the correlation with observed electrical properties. After effective interface engineering, low temperature electrical characterization revealed a significant increase in P ionization energy in samples with $H_{SOI}$ <= 15 nm, a result directly related to the dielectric mismatch.